hanbit hm d4m32m2g url:www.hbe.co.kr - 1 - hanbit electronics co.,ltd. rev.1.0 (august.2002) general description the hmd4m32m2 is a 4m x 32 bit dynamic ram high - density memory module. the module consists of two cmos 4m x 16 bit drams in 50 - pin tsop packages mounted on a 72 - pin. a 0.1 or 0.22uf decoupling capacitor is mounted on the printed circuit board for each dram components. the module is a single in - line memory module with edge connections and is intended for mounting in to 72 - pin edge connector sockets. all module components may be powered from a single 5v dc power supply. all inputs a nd outputs are ttl - compatible. features w part identification hmd4m32m2 ---- 4k cycles/64ms ref . solder HMD4M32M2G - 4k cycles/64ms ref . gold w access times : 50, 60ns w high - densi ty 16mbyte design w single +5v 0.5v power supply w jedec standard pinout w fp mode operation w ttl compatible inputs and outputs w fr4 - pcb design option s marking w timing 50ns access - 5 60 n s access - 6 w packages 72 - pin simm m presence detect pins pin 50ns 60ns pd1 vss vss pd2 nc nc pd3 vss nc pd4 vss nc performance range speed trac tcac trc thpc 5 50ns 13ns 90ns 26ns 6 60ns 15ns 110ns 30ns pin symbol pin symbol pin symbol 1 vss 25 dq2 2 49 dq 8 2 dq0 26 dq7 50 dq2 4 3 dq 16 27 dq2 3 51 dq 9 4 dq1 28 a7 52 dq 25 5 dq1 7 29 a11 53 dq1 0 6 dq2 30 vcc 54 dq2 6 7 dq 18 31 a8 55 dq1 1 8 dq3 32 a9 56 dq 27 9 dq 19 33 nc 57 dq1 2 10 vcc 34 nc 58 dq 28 11 nc 35 nc 59 vcc 12 a0 36 nc 60 dq 29 13 a1 37 nc 61 dq1 3 14 a2 38 nc 62 dq 30 15 a3 39 vss 63 dq1 4 16 a4 40 /cas0 64 dq3 1 1 7 a5 41 /cas2 65 dq1 5 18 a6 42 /cas3 66 nc 19 a10 43 /cas1 67 pd1 20 dq4 44 /ras0 68 pd2 21 dq2 0 45 nc 69 pd3 22 dq5 46 nc 70 pd4 23 dq2 1 47 /w e 71 nc 24 dq6 48 nc 72 vss 16mbyte(4mx32) 72 - pin simm fast page mode, 4k refresh, 5v part no. hm d4m32m2, HMD4M32M2G pin assignment
hanbit hm d4m32m2g url:www.hbe.co.kr - 2 - hanbit electronics co.,ltd. rev.1.0 (august.2002) functional block dia gram to all drams dq0 - dq7 dq8 - dq15 dq16 - dq23 dq24 - dq31 /ras0 /cas0 /cas1 /cas2 /cas3 /w e a0 - a11 /ras /lcas /ucas /oe /w a0 - a11 u 1 /ras /lcas /ucas /oe /w a0 - a11 u1 vcc vss 0.1uf or 0.22uf capacitor for each dram dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq0 d q1 dq2 dq3 dq4 dq5 dq6 dq7 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15
hanbit hm d4m32m2g url:www.hbe.co.kr - 3 - hanbit electronics co.,ltd. rev.1.0 (august.2002) absolute maximum rat ings parameter symbol rating voltage on any pin relative to vss v in ,out - 1v to 7.0v voltage on vcc supply relative to vss vcc - 1v to 7.0v power dissipation p d 2 w storage temperature t stg - 55 o c to 150 o c short cir cuit output current i os 50ma w permanent device damage may occur if " absolute maximum ratings" are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended dc opera ting conditions ( voltage reference to v ss , t a =0 to 70 o c ) parameter symbol min typ . max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.4 - vcc+1 v input low voltage v il - 1.0 - 0.8 v dc and operating cha racteristics symbol speed min max units - 5 - 880 ma i cc1 - 6 - 800 ma i cc2 - 16 ma - 5 - 880 ma i cc3 - 6 - 800 ma - 5 - 880 ma i cc4 - 6 - 800 ma i cc5 - 8 ma - 5 - 880 ma i cc6 - 6 - 800 ma i l(l) - 40 40 m a i o(l) - 5 5 m a v oh 2.4 - v v ol - 0.4 v i cc1 : operating current * (/ras , /cas , address cycling @t rc =min.) i cc2 : standby current ( /ras=/cas=v ih )
hanbit hm d4m32m2g url:www.hbe.co.kr - 4 - hanbit electronics co.,ltd. rev.1.0 (august.2002) i cc3 : /ras only refresh current * ( /cas=v ih , /ras, address cycling @t rc =min ) i cc4 : fast page mode current * (/ras=v il , /cas, address cycling @t pc =min ) i cc5 : standby current (/ras=/cas=vcc - 0.2v ) i cc6 : /cas - before - /ras refresh current * (/ras and /cas cycling @t rc =min ) i il : input leakage cu rrent (any input 0v v in 6.5v, all other pins not under test = 0v) i ol : output leakage current (data out is disabled, 0v v out 5.5v v oh : output high voltage level (i oh = - 5ma ) v ol : output low voltage level (i ol = 4.2ma ) * note : i cc1 , i cc3 , i cc4 a nd i cc6 are dependent on output loading and cycle rates. specified values are obtained with the output open. i cc is specified as an average current. in i cc1 and i cc3 , address cad be changed maximum once while /ras=v il . in i cc4 , addr ess can be changed maximum once within one page mode cycle. capacitance ( t a =25 o c, vcc = 5v, f = 1mz ) description symbol min max units input capacitance (a0 - a10) c in1 - 64 pf input capacitance (/w) c in2 - 70 pf input capacitance (/ras0) c in3 - 42 pf input capacitance (/cas0 - /cas3) c in4 - 30 pf input/output capacitance (dq0 - 31) c dq1 - 17 pf ac characteristics ( 0 o c t a 70 o c , vcc = 5v 10%, see notes 1,2.) - 5 - 6 standard operation symbol min max min max unit random read or write cycle tim e t rc 90 110 ns access time from /ras t rac 50 60 ns access time from /cas t cac 13 15 ns access time from column address t aa 25 30 ns /cas to output in low - z t clz 3 3 ns output buffer turn - off delay from /cas t c ez 3 13 3 15 ns transition tim e (rise and fall) t t 2 50 2 50 ns /ras precharge time t rp 30 40 ns /ras pulse width t ras 50 10k 60 10k ns /ras hold time t rsh 13 15 ns /cas hold time t csh 38 45 ns /cas pulse width t cas 8 10k 10 10k ns /ras to /cas delay time t rcd 20 37 20 45 n s /ras to column address delay time t rad 15 25 15 30 ns /cas to /ras precharge time t crp 5 5 ns
hanbit hm d4m32m2g url:www.hbe.co.kr - 5 - hanbit electronics co.,ltd. rev.1.0 (august.2002) row address set - up time t asr 0 0 ns row address hold time t rah 10 10 ns column address set - up time t asc 0 0 ns column address hold time t cah 8 10 ns column address hold referenced to /ras t ar 40 45 ns column address to /ras lead time t ral 25 30 ns read command set - up time t rcs 0 0 ns read command hold referenced to /cas t rch 0 0 ns read command hold referenced to /ras t rrh 0 0 ns write command hold time t wch 10 10 ns write command hold referenced to /ras t wcr 40 45 ns write command pulse width t wp 10 10 ns write command to /ras lead time t rwl 13 15 ns write command to /cas lead time t cwl 8 10 ns data - in set - up time t ds 0 0 ns data - in hold time t dh 8 10 ns data - in hold referenced to /ras t dhr 40 45 ns refresh period t ref 64 64 ns write command set - up time t wcs 0 0 ns /cas to /w delay time t cwd 36 40 ns /ras to /w delay time t r wd 73 85 ns /cas pre charge(c - b - r counter test) t cpt 20 20 ns column address to /w delay time t a wd 48 5 5 ns access time from /cas precharge t cpa 30 35 ns /cas precharge time (hyper page cycle) t cp 8 10 ns /ras pulse width (hyper page cycle) t rasp 50 200k 60 200k ns /w to /ras precharge time (c - b - r refresh) t wrp 10 10 ns /w to /ras hold time (c - b - r refresh) t wrh 10 10 ns notes 1. an initial pause of 200 m s is required after power - up followed by any 8 /ras - only or /cas - before - /ras refresh cycles before proper device operation is achieved. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times are measured between v ih(min) and v il(max) and are assumed to be 5ns for all inputs. 3. measured with a load equivalent t o 1ttl loads and 100pf 4. operation within the t rcd(max) limit insures that t rac(max) can be met. t rcd(max) is specified as a reference point only. if t rcd is greater than the specified t rcd(max) limit, then access time is controlled exclusively by t cac . 5. assu mes that t rcd 3 t rcd(max) 6. t ar , t wcr , t dhr are referenced to t rad(max) 7.this parameter defines the time at which the output achieves the open circuit condition and is not referenced to v oh
hanbit hm d4m32m2g url:www.hbe.co.kr - 6 - hanbit electronics co.,ltd. rev.1.0 (august.2002) or v ol . 8. t wcs , t rwd , t cwd and t awd are non restrictive ope rating parameter. they are included in the data sheet as electrical characteristic only. if t wcs 3 twcs(min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. 9. either t rch or t rrh must be satisfied for a read cycle. 10. these parameters are referenced to the /cas leading edge in early write cycles and to the /w leading edge in read - write cycles. 11. operation within the t rad(max) limit insures that t rac(max) can be met. t rad(max) is specified as a reference point only. if t rad is greater than the specified t rad(max) limit. then access time is controlled by t aa . timing diagram please refer to attached timing diagram chart (i)
hanbit hm d4m32m2g url:www.hbe.co.kr - 7 - hanbit electronics co.,ltd. rev.1.0 (august.2002) 0.25 mm max min 2.54 mm 1.27 mm gold : 1.04 0. 10 mm solder:0.914 0.10mm packaging informatio n sim m design o r dering information part number density org. package refresh cycle vcc speed HMD4M32M2G - 5 16mbyte 4mx 32bit 72 pin - simm 4,096 cycles 64ms ref. 5.0v 50ns HMD4M32M2G - 6 16mbyte 4mx 32 bit 72 pin - simm 4,096 cycles 64ms ref. 5.0v 60ns max 5.08 mm 1.2 7 0.08 mm 10.16 mm 107.95 mm 95.25 mm 6.35 mm r1.57 1.0 mm 6.35 mm 2.0 0 mm 1 9.00 mm 6.35 mm 101.19 mm r1.57 mm 3.18 0.51 r 3.38 mm gold : 1.04 10 mm
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